期末考改

module top;
system_clock #200 clock1(b);
system_clock #100 clock1(c);
system_clock #400 clock1(a);
system_clock #50 clock1(d);
number  n1(e,a,b,c,d);
endmodule

module number(e,a,b,c,d);
input a,b,c,d;
output e;
wire a1,b1,c1,d1,w1,w2,w3,w4;
nand(a1,a,a);
nand(b1,b,b);
nand(c1,c,c);
nand(d1,d,d);
nand(w1,b1,c1,d1);
nand(w2,c,d);
nand(w3,a,b,d);
nand(w4,a1,b1,c);
nand(e,w1,w2,w3,w4);
endmodule


module system_clock(clk);
parameter PERIOD=100;
output clk;
reg clk;
initial
clk=0;
always
begin
#(PERIOD/2)clk=~clk;
end
always@(posedge clk)
if($time>1000)
$stop;
endmodule

期末考

module top;
system_clock #200 clock1(b);
system_clock #100 clock1(c);
system_clock #400 clock1(a);
system_clock #50 clock1(d);
number  n1(e,a,b,c,d);
endmodule

module number(e,a,b,c,d);
input a,b,c,d;
output e;
wire a1,b1,c1,d1,w1,w2,w3,w4;
not(a1,a);
not(b1,b);
not(c1,c);
not(d1,d);
and(w1,b1,c1,d1);
and(w2,c,d);
and(w3,a,b,d);
and(w4,a1,b1,c);
or(e,w1,w2,w3,w4);
endmodule


module system_clock(clk);
parameter PERIOD=100;
output clk;
reg clk;
initial
clk=0;
always
begin
#(PERIOD/2)clk=~clk;
end
always@(posedge clk)
if($time>1000)
$stop;
endmodule

二位元多工器

module top;
wire A0, A1, B0, B1, SEL , NOT_SEL , X , Y , Z, W, OUT0, OUT1;
system_clock #1600clock1(A0);
system_clock #800clock2(A1);
system_clock #400clock3(B0);
system_clock #200 clock4(B1);
system_clock #100 clock5(SEL);
not n1(NOT_SEL, SEL);
and a1(X, A0, SEL);
and a2(Y, A1, SEL);
and a3(Z, B0, NOT_SEL);
and a4(W, B1, NOT_SEL);
or o1(OUT0, X , Z);
or o2(OUT1, Y , W);
endmodule
module system_clock(clk);
parameter PERIOD=100;
output clk;
reg clk;
initial clk=0;
always
 begin
#(PERIOD/2) clk=~clk;
 end
always@(posedge clk)
 if($time>2000)$stop;
endmodule

邏輯閘

module top;
  integer ia,ib;
  reg  a,b;
  wire out;

  or_behavioral or1(out,a,b);

  initial
    begin
      for (ia=0; ia<=1; ia = ia+1)
        begin
          a = ia;
          for (ib=0; ib<=1; ib = ib + 1)
            begin
              b = ib;
              #50 $display("a=%d b=%d out=%d",a,b,out);
            end
        end
    end
endmodule

module or_behavioral(out,a,b);
  input a,b;
  output out;
  wire a,b;
  reg out;

  always @(a or b)
    out = a | b;
endmodule

二位元多工器

module top;

wire[1:0] A, B, OUT;
wire SEL;
system_clock #200 clock1(A[0]);
system_clock #200 clock2(A[1]);
system_clock #100 clock3(B[0]);
system_clock #100 clock4(B[1]);
system_clock #400 clock5(SEL);
mux2 M1(OUT,A,B,SEL);

endmodule

module mux2(OUT, A, B, SEL);
output [1:0] OUT;
input [1:0] A,B;
input SEL;
mux hi (OUT[1], A[1], B[1], SEL);
mux lo (OUT[0], A[0], B[0], SEL);

endmodule

module mux(OUT, A, B, SEL);
output OUT;
input A,B,SEL;
not I5 (sel_n, SEL);
and I6 (sel_a, A, SEL);
and I7 (sel_b, sel_n, B);
or I4 (OUT, sel_a, sel_b);
endmodule

module system_clock(clk);
parameter PERIOD=100;
output clk;
reg clk;

initial clk=0;

always
 begin
#(PERIOD/2) clk=~clk;
 end

always@(posedge clk)
 if($time>1000)$stop;

endmodule

一位元多工器

module top;

wire A, B, SEL, OUT;
system_clock #400 clock1(A);
system_clock #200 clock2(B);
system_clock #100 clock3(SEL);

not I5 (sel_n, SEL);
and I6 (sel_a, A, SEL);
and I7 (sel_b, sel_n, B);
or I4 (OUT, sel_a, sel_b);

endmodule

module system_clock(clk);
parameter PERIOD=100;
output clk;
reg clk;

initial clk=0;

always
 begin
#(PERIOD/2) clk=~clk;
 end

always@(posedge clk)
 if($time>1000)$stop;

endmodule

3-輸入 2-AND邏輯閘

module top;

wire A, B, C, OUT,OUT2;
system_clock #400 clock1(A);
system_clock #200 clock2(B);
system_clock #600 clock3(C);


and a1(OUT, A, B);
and a2(OUT2, OUT, C);

endmodule

module system_clock(clk);
parameter PERIOD=100;
output clk;
reg clk;

initial clk=0;

always
 begin
#(PERIOD/2) clk=~clk;
 end

always@(posedge clk)
 if($time>1000)$stop;

endmodule