邏輯閘

module top;
  integer ia,ib;
  reg  a,b;
  wire out;

  or_behavioral or1(out,a,b);

  initial
    begin
      for (ia=0; ia<=1; ia = ia+1)
        begin
          a = ia;
          for (ib=0; ib<=1; ib = ib + 1)
            begin
              b = ib;
              #50 $display("a=%d b=%d out=%d",a,b,out);
            end
        end
    end
endmodule

module or_behavioral(out,a,b);
  input a,b;
  output out;
  wire a,b;
  reg out;

  always @(a or b)
    out = a | b;
endmodule